9-T FULL FOR LOW POWER DESIGN AT 22NM TECHNOLOGY

Abstract

This paper presents design of a new 9-transistors full adder which is simulated at 22nm CMOS technology. The design is based on a 3-transistor XOR Gate, two 2X1 multiplexers and a CMOS inverter. The main objectives to design this circuit are low power and small size of full adder. The design performance is analysed on Microwind Layout Editor on 22nm Fabrication Technology.