VERILOG IMPLEMENTATION OF A NODE OF HIERARCHICAL TEMPORAL MEMORY

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Published Oct 13, 2013
Pavan Vyas* , Mazad Zaveri

Abstract

The objective of this paper is to design, implement and analyze the node of the hierarchy temporal algorithm proposed by Jeff Hawkins. In this document, a design implementation of HTM algorithm node based on verilog hardware description language and mat lab programming language is proposed. The node is implemented using Xilinx Spartan-3e FPGA. The simulation results obtained with Xilinx ISE 10.1 software.
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Article Details

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Vol 3 No 7 (2013): Asian Journal of Computer Science And Information Technology
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Articles

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